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07/04/2016

HDL CODES FOR LOGIC GATES USING IF AND ELSE STATEMENTS

AND GATE:
entity and1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end and1;

architecture Behavioral of and1 is

begin
process (a,b)
begin
if (a='1' and b='1') then
c

01/06/2014

Up Down Counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity updowncount is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
dir : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (1 downto 0));
end updowncount;

architecture Behavioral of updowncount is

begin
process(clk,rst) is
begin
if rst='1' then q

31/05/2014

All gates VHDL and VERILOG

1. AND Gates

Verilog
two input and gate
module and2_1bit (a,b,c);
input a;
input b;
output c;
assign c = a&b;

endmodule

32 input and gates

module and2_32bit(a,b,c);
input [31:0] a;
input [31:0] b;
output [31:0] c;
assign c = a&b;
endmodule

° Semicolon after module declaration

° All signals in the Port List must be declared as either an input or output before they are used

° endmodule is one word and is not followed by a semicolon

30/05/2014

Counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cnt_bcddir is
port (
dout4 : out std_logic_vector(3 downto 0);
dir : in std_logic;
clk, arst, srst, en : in std_logic );
end;
-- ~ --
architecture Behavioral of cnt_bcddir is
-- declaration of signals inside this block
signal reg_cnt, nxt_cnt : std_logic_vector(3 downto 0);
begin
--
dff_cnt: process(arst, clk)
begin
if (arst = '1') then reg_cnt '0');
elsif (clk'event and clk = '1') then
if (srst = '1') then reg_cnt '0');
elsif (clk'event and clk = '1') then
else
if (en = '1') then
reg_cnt

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