Division of Computer Engineering - Datorteknik

Division of Computer Engineering - Datorteknik The division of Computer Engineering performs teaching and research on processor architectures and logic design.

Another paper.
13/03/2019

Another paper.

A direct digital-to-RF converter (DRFC) is presented in this work. Due to its digital-in-nature design, the DRFC benefits from technology scaling and …

The paper "Optimium Circuits for Bit-Dimension Permutations" by Mario Garrido, Jesus Grajal, and Oscar Gustafsson was ac...
06/02/2019

The paper "Optimium Circuits for Bit-Dimension Permutations" by Mario Garrido, Jesus Grajal, and Oscar Gustafsson was accepted to IEEE Transactions on VLSI Systems during the seasonal holidays and is now available as early access at

In this paper, we present a systematic approach to design hardware circuits for bit-dimension permutations. The proposed approach is based on decomposing a

29/11/2018

The paper "Optimization problem formulation for semi-digital FIR digital-to-analog converter considering coefficients precision and analog metrics" by M. Reza Sadeghifar, Oscar Gustafsson, and J. Jacob Wikner is now formally published and available for download.

If you happen to pass by Ajou University today. Welcome!
27/11/2018

If you happen to pass by Ajou University today. Welcome!

The paper "Optimization Problem Formulation for Semi-Digital FIR Digital-to-Analog Converter Considering Coefficients Pr...
12/11/2018

The paper "Optimization Problem Formulation for Semi-Digital FIR Digital-to-Analog Converter Considering Coefficients Precision and Analog Metrics" by M. Reza Sadeghifar, Oscar Gustafsson, and J. Jacob Wikner has been accepted to Analog Integrated Circuits and Signal Processing.

The paper "Obtaining Minimum Depth Sum of Products from Multiple Constant Multiplication" by Narges Mohammadi Sarband, O...
18/07/2018

The paper "Obtaining Minimum Depth Sum of Products from Multiple Constant Multiplication" by Narges Mohammadi Sarband, Oscar Gustafsson, and Mario Garrido was accepted to the IEEE Workshop on Signal Processing Systems (SiPS). This is Narges first publication, so a special congratulations to her!

Two papers accepted to Asilomar Conference on Signals, Systems, and Computers:Erik Bertilsson, Oscar Gustafsson, and Eri...
11/07/2018

Two papers accepted to Asilomar Conference on Signals, Systems, and Computers:

Erik Bertilsson, Oscar Gustafsson, and Erik G. Larsson, "A Modular Base Station Architecture for Massive MIMO with Antenna and User Scalability per Processing Node"

Madhur Gokhale, Cheolyong Bae, Oscar Gustafsson, and Mario Garrido, "Improved Implementation Approaches for 512-tap 60 GSa/s Chromatic Dispersion FIR Filters"

We are looking for a new professor.
04/07/2018

We are looking for a new professor.

Take your next step along your career path with us. Check out our job openings and apply directly!

The paper "Karatsuba with rectangular multipliers for FPGAs" by Martin Kumm, Oscar Gustafsson, Florent de Dinechin, Joha...
28/06/2018

The paper "Karatsuba with rectangular multipliers for FPGAs" by Martin Kumm, Oscar Gustafsson, Florent de Dinechin, Johannes Kappauf, and Peter Zipf won the best paper award at the IEEE Symposium on Computer Arithmetic!

18/04/2018

The paper "SFF - The Single-Stream FPGA-Optimized Feedforward FFT Hardware Architecture" by Carl Ingemarsson and Oscar Gustafsson was accepted to the special issue on Fast Fourier transform (FFT) hardware implementations of the Journal of Signal Processing Systems.

The paper shows that it is actually possible to further improve the impressive results on FFT implementation on FPGA from the earlier published, highly downloaded, paper "Efficient FPGA-Mapping of Pipeline SDF FFT Cores".

06/04/2018

The paper "Karatsuba with Rectangular Multipliers for FPGAs" by Martin Kumm, Oscar Gustafsson, Florent de Dinechin, Johannes Kappauf, and Peter Zipf was accepted to the IEEE Symposium on Computer Arithmetic, ARITH25.

The paper is a joint effort between German, Swedish, and French researchers and shows how the multiplication complexity for long word length multiplication can be reduced when using the rectangular multipliers present in Xilinx FPGAs.

In the newly released book "Arithmetic Circuits for DSP Applications" from IEEE Press/Wiley, Oscar Gustafsson and Lars W...
21/03/2018

In the newly released book "Arithmetic Circuits for DSP Applications" from IEEE Press/Wiley, Oscar Gustafsson and Lars Wanhammar have authored a chapter and Oscar has co-authored another.

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